1. Field of the Invention
The present invention generally relates to caching and more specifically to a multiprocessor system with caching on the memory side of a routing crossbar.
2. Description of the Related Art
Current multiprocessor systems include level 2 (L2) caches that are directly coupled to each processor. This configuration allows each processor to snoop writes to the caches of the other processors in the system and to access the caches with low latency compared with the number of clock cycles needed to retrieve data from system memory. System memory is typically accessed through a bridge device e.g., a Northbridge chip, and is shared with other devices in the system that are also coupled to the bridge device.
As the number of processors in multiprocessor systems increases, the complexity of the snooping and accessing of caches that are coupled to other processors increases. Therefore, the complexity and access latency increases as the parallelism increases.
Accordingly, what is needed in the art is a system and method for configuring caches in a multiprocessor system that allows for increased parallelism without increasing complexity and cache access latency.